Platform Technologies Characterizing Processor Architectures

Question: Discuss about the Platform Technologies for Characterizing Processor Architectures. Answer: B-Q1. Number System Id = MIT151492, so the value = 51492; A) Decimal to Hexadecimal 51492/16= 51492/16=3218, reminder 4 3218/16 = 201, reminder 2 201/16 =12, reminder 9 12/16 = 0, reminder 12 5149210 = C92416 B) Hexadecimal to Binary So the result will be, C 9 2 4 1100 1001 0010 0100 C92416 = 11001001001001002 C) Binary to Octal 001 100 100 100 100 100 1 4 4 4 4 4 11001001001001002 = 1444448 B-Q2. Processor clock speed vs Instructions per cycle (IPC): Processor clock speed or CPU clock rate define the speed of processor which is used to determine the execution of one or a bunch of instruction in a slot of time span (Crowley et al. 2014). CPU Clock cycles are used to regulate the execution of instruction sets and also creates a synchronized process to execute that instruction in a periodic way. The fastest computer processor with higher clock speed rate can execute more instruction in a single time span whereas a lower clock speed based processors can process minimum numbers of instruction in the same period (Warnock et al. 2015). CPU clock speeds are measured by the MHz (megahertz) or GHz (Gigahertz). CPU performances depend upon the clock cycle of CPU. Instruction per Cycle (IPC) is achieved by calculating the number of instructions are processed on a single CPU clock cycle (Thakur et al. 2013). Processor Clock rate is used to accumulate the speed ratio of a processor where IPC or instruction per cycle is used to determine the performances. As a maximum number of instruction which is processed by a processor is defined the efficiency of the processor. The IPC value can be maximized by the forming multi-process computing or parallel computing. Parallel computing uses a different mechanism rather than a singleton system. All the computing resources are shared to maximize the CPU clock cycle utilization. As an example, a simple processor processes the instruction as follows Fetch the instruction Decode the instruction Store on memory Location Execution of instruction Update program counter The above-described process is executed in a sequential manner but in the case of parallel computing, these process is distributed by the priority, access level, etc. which has better performance than traditional singleton computing system. The higher IPC reduce the throughput of a processor because multiple processing does not maintain the predefined way of execution sometimes it takes longer time than usual (Peng et al. 2013). Where if the instruction set follows the sequential manner the processor will utilize the maximum computing power on the specific instruction set. The technology over maximization of IPC depends on highly qualified engineering because the process of IPC maximization is achieved after the design of processor computing architecture. After that, there are multiple CPU cores, multiple cache memory block, and the pipelining process is used to gain the higher IPC rate (Ferdman et al. 2014). The main objective of this IPC maximization process is used to deal with the fixed rate processor clock cycle. The clock speed of CPU is not changeable due to its design restriction thats why peoples are trying to implement the most prominent way of multiple processing. Sometimes the higher rate of instruction per cycle can cause hardware breakdown of a system due to excessive workload. It is oblivious that the processor clock cycle or processors clock speed and the instruction per cycle or IPC efficiency level is totally opposite from each other. For getting the maximum performance, it is necessary to use these resource at an optimum level. B-Q3. Building of Computer System Building Of Computer System for Business Office Use Components Requirement Price CPU Intel Core i5-4460 CPU $188 Memory Corsair 8 GB DDR3 Memory $40 Hard Drives Seagate 1TB HDD SATA $50 Motherboard Gigabyte Intel Z170 ATX DDR3 Motherboards $134 Monitor Samsung 28-Inch UHD LED-Lit Monitor $370 Input Device Microsoft Ergonomic Keyboard for Business $70 Output Device HP Envy 4520 Wireless All-in-One Photo Printer with Mobile Printing $50 Expansion Capabilities Dual Graphics Card slots, Memory Slots Support for Multimedia Yes Costing Total Cost $902 Building of Computer System for Home Use Components Requirement Price CPU Intel Core I3-4160 Processor 3.60 GHz, 2-Core $118 Memory Samsung 2GB DDR2 RAM $11 Hard Drives Seagate 500 GB HD SATA $31 Motherboard Gigabyte Intel Micro ATX DDR3 Motherboard $45 Monitor HP 21.5-Inch IPS Monitor $99 Input Device Logitech Keyboard K120 $14 Output Device Canon MG2520 Color Photo Printer $30 Expansion Capabilities Single Graphics card slot ,Extra Memory Slots Support for Multimedia Yes Costing Total Cost $348 References Crowley, P., Fluczynski, M.E., Baer, J.L. and Bershad, B.N., 2014, June. Characterizing processor architectures for programmable network interfaces. InACM International Conference on Supercomputing 25th Anniversary Volume(pp. 287-298). ACM. Ferdman, M., Adileh, A., Kocberber, O., Volos, S., Alisafaee, M., Jevdjic, D., Kaynak, C., Popescu, A.D., Ailamaki, A. and Falsafi, B., 2014. A case for specialized processors for scale-out workloads.IEEE Micro,34(3), pp.31-42. Peng, S.Y., Huang, T.C., Lee, Y.H., Chiu, C.C., Chen, K.H., Lin, Y.H., Lee, C.C., Tsai, T.Y., Huang, C.C., Chen, L.D. and Yang, C.C., 2013. Instruction-cycle-based dynamic voltage scaling power management for low-power digital signal processor with 53% power savings.IEEE Journal of Solid-State Circuits,48(11), pp.2649-2661. Thakur, S., Rai, H.M., Kumar, S. and Pawar, S., 2013. Factors Determining the Speed and Efficiency of a Micro-Processor in a PC.International Journal of Emerging Trends in Electrical and Electronics (IJETEEISSN: 2320-9569),9(1). Warnock, J., Curran, B., Badar, J., Fredeman, G., Plass, D., Chan, Y., Carey, S., Salem, G., Schroeder, F., Malgioglio, F. and Mayer, G., 2015, February. 4.1 22nm Next-generation IBM System z microprocessor. In2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers(pp. 1-3). IEEE.